@article{Boriboon2020,

title = {Optimized design of QD-LD toward QD-SOA to achieve 35-dB maximum chip gain with 400-mA injected current},

author = {B Boriboon and D -R Worasucheep and A Matsumoto and K Akahane and N Yamamoto and N Wada},

url = {https://www.scopus.com/inward/record.uri?eid=2-s2.0-85087590569&doi=10.1016%2fj.optcom.2020.126238&partnerID=40&md5=79c7cac9cee99d79d73cbbb6ade45f23},

doi = {10.1016/j.optcom.2020.126238},

issn = {00304018},

year  = {2020},

date = {2020-01-01},

journal = {Optics Communications},

volume = {475},

publisher = {Elsevier B.V.},

abstract = {We measured the characteristics of Quantum Dot Semiconductor Optical Amplifiers (QD-SOA) with 25 stacked layers of InAs/InGaAlAs QDs grown on InP(311)B substrate. The temperature dependence of threshold current and lasing peak wavelength in C-band of QD-Laser Diode (QD-LD) were analyzed over its operating range of 15–80 °C. The chip gains of 3 device lengths (1.5, 2 and 2.4 mm) were compared under varied injected currents up to 500 mA. To avoid overheat and chip damage during measurements, the pulse current source with 1% and 10% duty cycles was used. Based on our best results of 2-mm long QD-SOA with 25 stacked QD layers, the 1% pulse is preferable because of its lower heating and additional chip gain of 11.9 dB. Hence, the highest chip gain of 35 dB was achieved at 400-mA injected current, as well as the highest 3-dB saturation output power at 20.9 dBm. According to the plot of chip gain versus wavelength, it shows 3-dB gain spectrum over 20 nm and the highest peak at 1570-nm wavelength with 500-mA injected current. In addition, the results of another QD-SOA module showed 15.4-dB Input Power Dynamic Range (IPDR), faster response time due to less pattern effect and error-free transmission of 40 Gb/s data over 20-km Single Mode Fiber (SMF) link. © 2020 Elsevier B.V.},

note = {cited By 0},

keywords = {},

pubstate = {published},

tppubtype = {article}

}

@article{Worasucheep2011,

title = {Design and performance of 10 Gb/s optical receiver in 50-Ghz DWDM transmission over 40-km SSMF},

author = {D -R Worasucheep and W Srisuwarat and J Akaranuchat},

url = {https://www.scopus.com/inward/record.uri?eid=2-s2.0-80055085031&partnerID=40&md5=532d38c14af1f26c179a9fe4b9ff75a0},

issn = {16859545},

year  = {2011},

date = {2011-01-01},

journal = {ECTI Transactions on Electrical Engineering, Electronics, and Communications},

volume = {9},

number = {1},

pages = {157-168},

publisher = {ECTI Association},

abstract = {This paper describes the design of 10 Gb/s optical receiver, which consists of an Avalanche Photo-Detector (APD) and a Clock & Data Recovery (CDR) circuit. All components are successfully integrated onto the 4-layered FR-4 PCB, using two types of signal paths: differential microstrip and single-ended CB-CPW. Their dimensions are optimally chosen for matching impedance, according to the ADS simulations. The receivers performance has been evaluated under 3 impairments: jitter, interchannel crosstalk and fiber dispersion. The Periodic Jitter (PJ) is added to analyze histograms and measure the receivers jitter tolerance. The crosstalk and dispersion effects on eye-diagram are demonstrated via the testbed of 50-GHz Dense Wavelength Division Multiplexing (DWDM) transmission over 40-km Standard Single Mode Fiber (SSMF). The measured jitter tolerance proves that this receiver can pass the SONET (Synchronous Optical NETwork) mask standard with Bit Error Rate (BER) below 10-12. The recovered eye-diagrams show that this design can reduce both crosstalk and dispersion effects. The power penalty of this receiver is determined from the BER plot to be within 2-dB standard limit.},

note = {cited By 0},

keywords = {},

pubstate = {published},

tppubtype = {article}

}